Vertically integrated flash memory cell and method of fabricating a vertically integrated flash memory cell

ABSTRACT

A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a pair of floating gates is fabricated within a trench in a substrate. The floating gates are fabricated using sidewall spacers within the trench. A doped region is buried at the bottom of the trench. The structure can be fabricated such that the buried doped region provides a connecting layer in a multi-bit flash memory cell. Alternatively, the buried doped region may be used as a buried bitline in a single bit flash memory cell.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to a unique cellstructure for use in flash memory and, more particularly, to avertically integrated flash memory cell which implements a pair offloating gates fabricated as sidewall spacers within a trench and to amethod for fabricating the memory cell.

[0003] 2. Description of the Related Art

[0004] This section is intended to introduce the reader to variousaspects of art that may be related to various aspects of the presentinvention, which are described and/or claimed below. This discussion isbelieved to be helpful in providing the reader with backgroundinformation to facilitate a better understanding of the various aspectsof the present invention. Accordingly, it should be understood thatthese statements are to be read in this light, and not as admissions ofprior art.

[0005] Electronic memory comes in a variety of forms and may be used fora variety of applications. One type of commonly used memory is flashmemory. Flash memory is a solid state storage device which provides easyand fast information storage. Flash memory is a type of electricallyerasable programmable read-only memory (EEPROM) that can be erased andprogrammed through exposure to an electrical charge. Flash memory allowsdata to be written or erased in blocks rather than one byte at a time aswith typical EEPROM devices, thereby making flash memory considerablyfaster.

[0006] Flash memory generally includes a grid of columns and rowsforming an array of flash memory cells. Each cell generally comprisestwo transistors separated by a thin oxide layer. One of the transistorsserves as the floating gate while the other serves as the control gate.The floating gate is coupled to the row or wordline through the controlgate. Single data bits or multiple data bits can be stored in the memorycells by placing various levels of charge on the floating gate of thecell transistor. By storing differing levels of charge and thusobtaining different levels of threshold voltage V_(t), a cell can storemore than one bit of information therein. For example, to facilitate thestorage of two binary bits, four levels of charge and correspondinglevels of V_(t) may be used. During a read operation, a decoder sensesthe transition threshold V_(t) to determine the corresponding binaryvalue of the multi-bit information (e.g. 00, 01, 10, 11).Disadvantageously, storing higher densities of binary bits in each cellto increase the number of voltage levels V_(t) used to store the higherbit densities introduces problems in the memory array including a higheroperating voltage, more power dissipation, and increased circuitcomplexity for reading, erasing, and decoding the binary information.Further, if the number of charge levels increases without increasing thesupply voltage, it becomes increasingly difficult to detect anddistinguish the correct stored charge levels.

[0007] One technique for alleviating some of the problems associatedwith the storage of the multi-bit binary information in a memory cell isto provide two separate floating gates for each transistor within thememory cell. The control gate of the transistor is connected to awordline provided over both floating gates while each of the source anddrain regions of the transistor are connected to respective digit lines.Dual floating gate transistors distribute or partition the total chargein the transistor over each of the two floating gates, rather than asingle floating gate. One advantage of dual floating gate transistors isthat the dual floating gates allow for better control of the totalcharge in the transistor, as can be appreciated by those skilled in theart.

[0008] The processing of such structures is often costly and complex,especially with ever-increasing demands for smaller structures.Providing multi-bit flash cells and single bit flash cells incorporatingdual floating gate patterns with less cumbersome and less costlyprocessing techniques would be advantageous.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Advantages of the invention may become apparent upon reading thefollowing detailed description and upon reference to the drawings inwhich:

[0010]FIG. 1 illustrates the electrical schematic of a memory cellconstructed in accordance with the present techniques;

[0011]FIG. 2 illustrates a top view of the topology of the memory cellconstructed in accordance with the present techniques;

[0012]FIG. 3 illustrates an electrical schematic of an array of memorycells arranged in accordance with the present techniques;

[0013]FIGS. 4A and 4B represent timing diagrams for activating the digitlines and row lines to write binary data “01” or “10” into the memorycell illustrated in FIGS. 1-3;

[0014]FIGS. 5A, 5B, and 5C illustrate the timing diagrams for activatingthe digit lines and row line to write binary data “11” into the memorycell illustrated in FIGS. 1-3;

[0015]FIGS. 6A, 6B, and 6C illustrate the timing diagrams for activatingthe digit lines and row line to read a stored multi-bit binary valuefrom the memory cell illustrated in FIGS. 1-3;

[0016] FIGS. 7-15 illustrate the steps for constructing a multi-bitmemory cell in accordance with a first fabrication technique; and

[0017]FIGS. 16 and 17 illustrate the steps for constructing a single-bitmemory cell in accordance with a second fabrication technique.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0018] One or more specific embodiments of the present invention will bedescribed below. In an effort to provide a concise description of theseembodiments, not all features of an actual implementation are describedin the specification. It should be appreciated that in the developmentof any such actual implementation, as in any engineering or designproject, numerous implementation-specific decisions must be made toachieve the developers' specific goals, such as compliance withsystem-related and business-related constraints, which may vary from oneimplementation to another. Moreover, it should be appreciated that sucha development effort might be complex and time consuming, but wouldnevertheless be a routine undertaking of design, fabrication, andmanufacture for those of ordinary skill having the benefit of thisdisclosure.

[0019]FIG. 1 illustrates a memory cell constructed in accordance withthe teachings of the present techniques. The memory cell is formed of aMOSFET transistor 10 having respective source and drain regions 12 and14, a pair of floating gates 16 and 18, and a control gate 20 providedover both floating gates 16 and 18. The source 12 is respectivelyconnected to a first digit (column/bit) line 22, and the drain 14 isrespectively connected to a second digit line 24. The control gate 20 isconnected to a row (word) line 26.

[0020] The manner in which the transistor shown in FIG. 1 is integratedinto a memory array is illustrated in FIGS. 2 and 3, where FIG. 2illustrates the electrical connection of the FIG. 1 transistor 10 into amemory array and FIG. 3 illustrates in schematic form a top view of aportion of a silicon substrate containing a portion of the memory array.

[0021]FIG. 2 shows a memory cell 28 which contains the transistor 10structure shown in FIG. 1. Row line 26 extends over respective floatinggate regions 16 and 18. Digit lines 22 and 24, which are perpendicularto row line 26, are also illustrated as respectively extending over, andconnecting with, source and drain regions 12 and 14. Each transistor isthus controlled by voltages applied to the row line 26 which covers bothfloating gates 16 and 18 and the respective digit lines 22 and 24electrically connected to source and drain regions 12 and 14.

[0022] It should be noted that although the above description referencesregion 12 as a source and region 14 as a drain, in fact, during theprogramming and readout operations, transistor 10 is operated so thateach of regions 12 and 14 operate at one time or another as a source ora drain. Accordingly, for purposes of further discussion it should berecognized that whenever a region is identified as a source or a drainregion, it is only for convenience. During operation of the transistoreither region 12 or 14 could be a source or a drain depending on themanner in which the transistor is being controlled by voltages appliedto the row line 26 and digit line 22 and 24 conductors.

[0023]FIG. 2 further illustrates, in block diagram format, a circuit 30.The circuit 30 forms part of an electric circuit which supplies thevoltage control signals to the row conductor 26 during execution of aread, write, or erase operation. The row conductor 26 cooperates withdigit lines 22 and 24, which are in turn activated by a digit linedriver and sense amplifier circuit 32, which is also part of an electriccircuit for supplying the voltage control signals to the digit lines 22,24 during execution of a read, write or erase operation. The circuit 32is connected to a timing block 34 that is run off a clock (not shown) asillustrated in FIG. 3.

[0024] The electrical schematic connection of a memory array having aplurality of cells 28 is illustrated in greater detail in FIG. 3. Eachtransistor in the array is shown in greater detail as is the connectionto the row decoder and RWE circuit 30, the timing block 34, the odd (0)and even (E) digit lines 22, 24 and the digit line driver and senseamplifier circuit 32. The circuit 32 connected to a multi-bit decodercircuit 36. The function of decoder 36 is to decode the voltages whichare sensed by the sense amplifiers in the circuit 32 on the odd and evendigit lines 22 and 24 when a particular memory cell is read to therebydecode the value of the multi-bit information stored within the memorycell. The decoded multi-bit binary value (e.g. 00, 01, 10, 11 for atwo-bit cell) is supplied out of the decoder block 36 as read data 38.The multi-bit decoder circuit 36 is also connected to a digit linedecoder circuit 40 that decodes digit line addresses 42 for reading andwriting information from and to a particular memory cell transistor 10.Digit line decoder circuit 40 also has a data input 44 that is used toprogram data into the memory cell transistor 10 as will be described indetail below. The row decoder also contains a row address input 46 aswell as an RWE input from a programming state device 48, i.e. a memorycontroller, which determines which of the read, write, and erase memoryoperations is to be performed so that both the row decoder and RWEcircuit 30 and digitline driver and sense amplifier circuit 32 areappropriately operated to execute either a read, write, or eraseoperation. The row decoder and RWE function circuit 30 is shown asconnected to row lines 26 through respective driver amplifiers 50.

[0025] As noted earlier, the present technique utilize a pair offloating gates 16 and 18 in each memory cell transistor 10 to storecharges representing the multi-bit binary data that is stored in eachmemory cell. For ease of subsequent discussion, assume that two binarybits of information are to be stored in each memory cell, i.e., one ofthe four states 00, 01, 10, and 11. In the following discussion, thevoltages and timing signals are similar to the voltages and timingsignals typically used in operation of a single floating gatetransistor. Thus, the dual floating gate cell is able to store multi-bitbinary data in a cell which operates in a manner which is similar to aconventional flash memory cell.

[0026] The programming of a memory cell to write a 01 or 10 state isillustrated in FIGS. 4A and 4B. The signal relationship is shown whenFIGS. 4A and 4B are considered together. FIG. 4A represents the timingof a voltage which is applied to one of the digit lines (odd or even) bythe digit line driver and sense amplifier circuit 32 depending onwhether the incoming data 44 is to be stored as a 01 or 10 condition. Asshown in FIG. 4A, a pulse having a duration in the range of 2 to 10microseconds, such as approximately 4 microseconds (μs) duration, and ata level of approximately 5 volts, is applied to a digit line 22, 24(again either odd or even depending on whether the programmed conditionis 01 or 10) while at the same time, row line 26 has a pulse appliedthereto of approximately 10 volts for a period in the range of 20-100microseconds , such as approximately 60 microseconds (μs). As shown inFIGS. 4A and 4B, the row voltage is applied first, followed by thedigitline voltage approximately 60 nanoseconds (ns) later. Theoverlapping voltages applied to the row line and digit line create avoltage differential across a floating gate to which the digit linecorresponds causing the floating gate to store a charge.

[0027]FIGS. 5A, 5B, and 5C illustrate the timing diagrams for writing a11 state into a memory cell transistor 10. As shown in FIG. 5A, the evendigit line, e.g. digit line 24, has a pulse in the range of 2 to 10microseconds, such as approximately 3 microseconds (μs) applied thereto,while at the same time the row line has approximately 10 volts appliedthereto. The digit line 24 pulse occurs after the beginning of the rowline pulse. This charges the floating gate associated with even digitline 24. After the digit line 24 is deactivated for approximately 60 ns,then the odd digit line 22 is activated for 2 to 10 microseconds, suchas approximately 5 microseconds (μs). During this period, the row line26 remains active throughout a period in the range of 20 to 100microseconds such as approximately, 60 microseconds (μs). In thismanner, both digit lines are activated in sequence while the row line isactivated to cause the differential voltage between the row line andeach digit line to store a charge in each of the floating gate regions16 and 18.

[0028] The manner in which stored charges can be read out from thetransistor 10 is illustrated in FIGS. 6A, 6B and 6C. During a readoperation, each of the digit lines is again activated, but this time, ata much lower voltage. As shown in FIGS. 6A and 6B, the digit lines haveapproximately 0.8 volt applied thereto. Again, this voltage is appliedin sequence so that first the even digit line 24 has the voltage appliedfor a period in the range of 2 to 10 milliseconds (ms) such asapproximately 3.5 milliseconds, following which, the odd digit line 22has the same voltage applied for a period in the range of 2 to 10milliseconds such as approximately 3.5 milliseconds, so that in total,approximately 7 milliseconds are implemented for a read operation.During the entire time that the even and odd digit lines 24 and 22 aresequentially activated, the row line is activated with a higher voltageof approximately 5 volts for a period in the range of 20-100milliseconds and such as approximately 60 milliseconds creating adifferential voltage across the corresponding floating gates. Thisdifferential voltage between the row line 26 and each of the respectivedigit lines 22, 24 causes a read out through the sense amplifiers withinthe digitline driver and sense amplifier circuit 32 (FIG. 3) of avoltage value corresponding to the respective charges stored in each ofthe two floating gates 16 and 18 for each transistor 10. The outputvoltages from the respective even and odd digit lines are applied to thedecoder 36 illustrated in FIG. 3 from the sense amplifiers. The decoder36 takes the two voltages from the odd and even digit lines (22 and 24)and determines which of the states 00, 01, 10, or 11 was previouslystored in the transistor 10. This data is then output via bus 38 fromthe decoder 36.

[0029] Each memory cell which is selected for either a write or read ofdata is addressed by the row decoder 30 and digit line decoder 40 in aconventional fashion. Accordingly, a detailed discussion of how row anddigit address decoders operate will not be provided herein. Suffice itto say that when a digit line is addressed, there are two digit lines(odd and even) that are activated in sequence for a read operation andfor writing the 11 state, while one or the other of the digit lines isactivated for writing a 01 or 10 value into the memory cell.

[0030] Data is erased from transistor 10 by applying differentialvoltages across the row and digit lines in a manner which causes thecharges stored within the floating gates to either tunnel to thedigitlines or tunnel to the substrate. This restores the cell to a 00state. In the case of the former, a voltage differential is applied bysetting the row voltage to approximately zero volts while the digitlines are set at approximately 10 volts. By doing this, the electronsthat are stored at the floating gate are attracted and tunnel to thedigit line positive potential. Also, during the erase cycle, the digitlines alternate so that first the even 24 and then the odd 22 (orvice-versa) digit lines have the approximately 10 volts applied to them,while the row conductor (word line 26) remains at approximately zerovolts. It is also possible to set the digit lines 22, 24 at a lowervoltage, for example, 6 volts, while the word line 26 has approximately4 volts applied to it. The differential voltage across the floating gateregions 16, 18 is still approximately 10 volts as before and erasure ofthe floating gate region charges will occur.

[0031] An alternative way to erase the memory cells is to have theelectrons tunnel to the substrate from the two floating gates 16, 18.For this to occur, the erase can be accomplished by applyingapproximately 10 volts to the substrate while the word line 26 is set atapproximately zero volts.

[0032] The timing diagrams described with reference to FIGS. 4A-4B,5A-5C, and 6A-6C are further summarized in Table 1 below. Althoughrepresentative voltages and timing patterns have been described forwriting, reading, and erasing a memory cell, these are merely exemplary.Many changes and modifications can be made to produce, write, read, anderase signals which are equivalent to those described above and whichcan be used in an equivalent manner to operate the memory celltransistor 10 in the write, read and erase modes. TABLE 1 ProgrammingVDL VDL DL Pulse RL Pulse State Function even VRL odd duration LeadingEdge Duration ″OO″ Read .8V/0V  5V 0V/.8V 3 ms 1st DLE leading 60 msedge is 60 us from RL leading edge and the 2nd DLO leading edge is .5 usfrom the 1st DLE trailing edge. RL trailing edge is 55 ms from the 2ndDLO trailing edge. Write  0V  0V  0V None None None Erase* 10V  0V 10V50 ms by Alternate the DL D.C. Blocks pulses ″O1″ Read  0V  5V .8V 3 ms1st DLE leading 60 ms edge is 60 us from RL leading edge and the 2nd DLOleading edge is .5 us from the 1st DLE trailing edge. RL trailing edgeis 55 ms from the 2nd DLO trailing edge. Write float 10V  5V 4 us 60 nsafter RL 60 us Erase* 10V  0V 10V 50 ms by Alternate the DL D.C. Blockspulses ″1O″ Read .8V  5V  0V 3 ms 1st DLE leading 60 ms edge is 60 usfrom RL leading edge and the 2nd DLO leading edge is .5 us from the 1stDLE trailing edge. RL trailing edge is 55 ms from the 2nd DLO trailingedge. Write  5V 10V float 4 us 60 ns after RL 60 us 50 ms Alternate theDL Erase* 10V  0V 10V Blocks pulses D.C. ″11″ Read .8V/0V  5V 0V/.8V 3ms 1st DLE leading 60 ms edge is 60 us from RL leading edge and the 2ndDLO leading edge is .5 us from the 1st DLE trailing edge. RL trailingedge is 55 ms from the 2nd DLO trailing edge. Write  5V 10V  5V 4 us 1stDL pulse 60 ns 60 us after RL leading edge and 2nd DL pulse 60 ns after1st DL trailing edge Erase* 10V  0V 10V 50 ms by Alternate the DL D.C.Blocks pulses

[0033] Techniques for fabricating transistor 10 having floating gates 16and 18 will now be described with reference to FIGS. 7-17. A firstfabrication technique of providing a multi-bit flash memory cell isdescribed with reference to FIGS. 7-15, while a second fabricationtechnique of providing a single-bit memory cell is described withrespect to FIGS. 16 and 17. Advantageously, the present techniquesincorporate vertically integrated memory cell technology, as can beappreciated by those skilled in the art.

[0034]FIG. 7 illustrates a P-doped silicon (Si) substrate 52. Thesubstrate 52 includes a U-shaped trench 54 in which the transistor 10will be vertically fabricated. The trench 54 may be formed through anyone of a number of commonly known wet or dry etching techniques such asplasma etching, ion beam etching, or reactive ion etching (RIE). Thetrenches may have a depth in the range of about 0.15 microns about 0.45microns, for example. Advantageously, the trench 54 may be “U-shaped.”By eliminating the hard edges that would exist in a more angular trenchhaving sharp edges where the sidewalls of the trench intersect the floorof the trench, the threshold voltage of the device may be less affectedby the trench shape. FIG. 7 also includes an oxide layer 56, such assilicon dioxide, which has been applied on top of the surface of thesubstrate 52 including the surface of the trench 54 by chemical vapordeposition (CVD), for example. It should be understood that thoseskilled in the art readily understand the deposition, masking, andetching techniques used to construct the structure illustrated in FIG.7.

[0035]FIG. 8 illustrates the structure of FIG. 7 after the substrate 52has been doped. Each of the N+ regions 58, 60 and 62 may be formed by asuitable doping technique, such as ion implantation, as can beappreciated by those skilled in the art. The N+ region 58 willeventually form the source 12 (or drain 14, depending on mode ofoperation) of the transistor 10. Similarly, the N+ region 60 will formthe drain 14 of the transistor 10. The N+ region 62 may be implementedto reduce the effects of angled edges of a trench on the thresholdvoltage. However, as described above, because the trench 54 is U-shaped,the N+ contact region 62 may be omitted in the present exemplaryembodiment. Alternatively, the buried N+ region 62 may be used as aburied digit or bit line if the transistor 10 is fabricated into asingle-bit flash memory cell. Each of these options is discussed ingreater detail below. Advantageously, the N+ regions 58, 60 and 62 areformed using a high-dosage of N+ dopents using low energy implantation,such as about about 500 eV, for example.

[0036]FIG. 9 illustrates the structure of FIG. 8 after the deposition ofa polysilicon layer 64. A photoresist layer 66 is applied for thepurpose of etching the polysilicon layer 64 to form polysilicon rows(illustrated in FIGS. 12-15). The polysilicon layer 64 is disposedthrough the trench 54 in a direction that will be ultimatelyperpendicular to the direction of the word line. As will be illustratedfurther with respect to FIGS. 12-15, the polysilicon layer 64 ispatterned to provide a plurality of rows perpendicular to the word line.The photoresist layer 66 is patterned using a mask such that once thepolysilicon layer 64 it etched, isolated rows are formed (FIG. 12-15).After the rows are formed, the photoresist layer 66 may be removed via achemical rinse, for example.

[0037]FIG. 10 illustrates the structure of FIG. 9 after formation of therows and after the polysilicon layer 64 has been selectively etched toform sidewall spacers. In the present embodiment, the spacer etchingprocess is selective to the oxide layer 56 such that the oxide layer 56forms an etch-stop layer during the etching of the polysilicon layer 64.The polysilicon layer 64 is etched to form polysilicon spacers 64A and64B. As previously described, the spacers 64A and 64B are electricallyisolated from each other within the memory cell 28 (FIG. 2) therebyforming the floating gates 16 and 18 of the transistor 10.

[0038] Next, a gate oxide layer, such as an ONO (oxide, nitride, oxide)layer 68, is applied over the substrate 52. The ONO layer 68 forms thethin oxide layer between the control gate 20 (FIG. 1) and the floatinggates 16, 18 used to enable the functionality of the transistor 10, ascan be appreciated by those skilled in the art. As previously describedand discussed further below, a word line will be formed on the ONO layer68, thereby serving as the control gate 20 of the transistor 10.

[0039]FIG. 11 illustrates the formation of the word line 26 (FIG. 1) inthe trench 54. As previously described, the word line 26 provides thecontrol gate 20 for the transistor 10. A doped polysilicon material 71is disposed on top of the ONO layer 68 such that it fills the trench 54entirely. The width of the word line 26 may be greater than the width ofthe trench. The surface of the polysilicon material 71 (word line 26)may then be planarized, such as by chemical mechanicalpolishing/planarization (CMP). After CMP, a metal layer, such as atungsten (W) layer 72 may be disposed on the polysilicon material 71(word line 26). The tungsten (W) layer 72, may be disposed by physicalvapor deposition (PVD) or chemical vapor deposition (CVD), for example.Other suitable metals may be used in the metal layer, including, but notlimited to copper, gold, tin, aluminum, nickel, titanium, and the like.

[0040] During fabrication of the memory cell, portions of thepolysilicon material 71 may diffuse into the metal layer, here tungsten(W) layer 72, thereby reducing the conductivity of the polysiliconmaterial 71. To prevent the diffusion of impurities from polysiliconlayer 71 into the tungsten (W) layer 72, a barrier layer, such astungsten nitride (WN_(x)) layer 70, may be disposed between thepolysilicon material 71 and the tungsten (W) layer 72. While thetungsten nitride (WN_(x)) layer 70 electrically connects the tungsten(W) layer 72 to the polysilicon material 71, it also inhibits thediffusion of impurities from the polysilicon material 71 into thetungsten (W) layer 72 and protects the polysilicon material 71 duringfurther processing, as can be appreciated by those skilled in the art.The tungsten nitride (WN_(x)) layer 70 may be deposited by physicalvapor deposition (PVD) or by chemical vapor deposition (CVD), forexample. As with the tungsten (W) layer 72, other suitable materials maybe used for the barrier layer, including, but not limited to titaniumnitride, for example. Further, the barrier layer may be omittedcompletely.

[0041] Finally, a nitride layer 74, such as silicon nitride (Si₃N₄) maybe disposed on top of the tungsten layer 72 to prevent oxidation of theunderlying metal layer during subsequent processing of the memory cell.As can be appreciated, various other common insulating materials such assilicon oxide (SiO₂), may be used instead of the nitride layer 74 or incombination with the nitride layer 74. The nitride layer 74 may bedeposited by chemical vapor deposition (CVD), for example. Subsequently,conventional processing steps are applied to the structure of FIG. 11 toform the metal interconnect patterns using photoresist, alloying,passivation layers and bond pad pattern etching to complete theintegrated circuit die, as can be appreciated by those skilled in theart.

[0042]FIG. 12 is a partial cross-sectional plan view of a number oftransistors 10 formed by the process described above. FIG. 12 isprovided to illustrate better the rows and columns of the memory arraydescribed with reference to FIGS. 2 and 3. The row 76 is illustratedwithout a polysilicon word line 26 to illustrate better the trench 54and the spacers 64A and 64B which form the floating gates 16 and 18(FIG. 1) of the transistors 10, as previously described. The row 78 isillustrated with the polysilicon material 71 (word line 26). In thememory array, the transistors 10 share a common N+ region 58 or 60 witha transistor in the adjacent row. Here, the transistors 10 in row 76 andthe transistors 10 in row 78 share a common N+ region illustrated hereas a common source 12, for example. As can be appreciated, the othercorresponding rows (not illustrated) directly adjacent to the rows 76and 78 share respective common N+ regions 60. The N+ regions 58 and 60provide the first digit line 22 and the second digit line 24, aspreviously described.

[0043] As illustrated with reference to FIG. 12, the dual floating gatetransistors 10 are formed within the trenches 54. Each pair ofpolysilicon spacers 64A and 64B are separated by an oxide region whereinthe polysilicon layer 64 was etched down to the oxide layer 56. FIGS.13-15 illustrate an exemplary process of creating the polysilcon spacers64A and 64B in accordance with the present technique. Specifically,FIGS. 13-15 illustrates a partial cross-sectional plan view of thesubstrate 52 taken along the cross-sectional line 13-13 of FIG. 12. Aspreviously described, a trench 54 is formed in the substrate 52. Thesubstrate 52 includes the oxide layer 56 and the polysilicon layer 64which will be etched to form the spacers 64A and 64B. For simplicity,the doped N+ regions 58, 60 and 62 are not illustrated in FIGS. 13-15,although they may be present at this point in the processing, aspreviously described.

[0044] As previously described, the polysilicon layer 64 is etched usinga photoresist layer 66 patterned to form the columns of the memory arrayby separating each of the transistors 10 in a respective row (e.g. eachof the transistors 10 of row 76 or row 78 from adjacent transistors inthe respective row). Thus, the photoresist 66 is applied across thesubstrate 52 in strips, as illustrated in FIG. 13. Once the patternedphotoresist 66 is disposed on the surface of the polysilicon layer 64,it is exposed and developed to etch the underlying polysilicon layer 64,leaving the pattern illustrated in FIG. 14. As illustrated, the area 80wherein the patterned photoresist layer 66 was disposed (FIG. 13) hasbeen etched such that the polysilicon layer 64 has been removed, therebyleaving a layer of exposed oxide 56. The area 80 will eventually formthe separation areas between the adjacent spacers in a row. Conversely,in the area 82 wherein the patterned photoresist layer 66 was notdisposed on the polysilicon layer 64, the polysilicon layer 64 remains.The remaining polysilicon layer 64 is then etched (selective to theoxide layer 56) to provide the spacers 64A and 64B as previouslydescribed and further illustrated in FIG. 15. As can be appreciated bythose skilled in the art, there are a number of techniques that may beused to form the dual floating gate multi-bit vertically integratedtransistors 10 described herein.

[0045]FIGS. 16 and 17 illustrate an alternate embodiment implementingthe present techniques. The embodiment described with reference to FIGS.16 and 17 illustrates a single bit flash memory cell incorporating aburied bit line. The structure illustrated with reference to FIG. 16illustrates the same features discussed with reference to FIGS. 9 and10. Accordingly, the substrate 52 includes a trench 54, an oxide layer56, N+ regions 58, 60 and 62, polysilicon spacers 64A and 64B and an ONOlayer 68. In the present exemplary embodiment, the N+ region 62 extendsthroughout the length of the trench 54. Conversely, the N+ contactregions 58 and 60 are isolated regions that are each adjacent to arespective sidewall spacer 64A and 64B.

[0046] During the etching of the polysilicon layer 64 to form thepolysilicon spacers 64A and 64B, the oxide layer 56 may also be etchedsuch that the oxide at the bottom of the trench 54 is depleted orcompletely removed. In one exemplary embodiment, the etchant used toetch the polysilicon layer 64 is not selective to oxide. Accordingly,the oxide layer 56 may be etched at the bottom of the trench 54, alongwith the polysilicon layer 64. After the formation of the polysiliconspacers 64A and 64B, the oxide layer 56 may be re-disposed such that itcovers the bottom of the trench 54. The oxide layer 56 may bere-disposed at a greater thickness than originally disposed to providebetter isolation between the wordline and the buried bitline formed bythe N+ contact region 62. As illustrated in FIG. 16, the ONO layer 68and the oxide layer 56 have been disposed through the trench 54 afterthe formation of the polysilicon spacers 64A and 64B.

[0047] As previously described with reference to FIG. 11, a dopedpolysilicon material 71 is disposed on top of the ONO layer 68 such thatit fills the trench 54 entirely. However, because the polysiliconmaterial 71 is now used to form a bitline, the polysilicon material 71is not etched to extend through the entire length of the trench 54.Instead, the polysilicon material 71 will be etched to form rows whichare isolated from adjacent rows formed down the length of the trench 54,as can be appreciated. As previously described, a metal layer, such as atungsten (W) layer 72 may be disposed on the polysilicon material 71. Toprevent the diffusion of impurities from the polysilicon material 71into the tungsten (W) layer 72, a barrier layer, such as tungstennitride (WN_(x)) layer 70, may be disposed between the polysiliconmaterial 71 and the tungsten (W) layer 72, as previously described.Finally, a nitride layer 74, such as silicon nitride (Si₃N₄) may bedisposed on top of the tungsten layer 72 to prevent oxidation of theunderlying metal layer during subsequent processing of the memory cell.Subsequently, conventional processing steps are applied to the structureof FIG. 17 to form the metal interconnect patterns, as previouslydescribed with reference to FIG. 11. However, as previously discussedwith reference to the polysilicon material 71 of the present embodiment,each of the wordline stack layers are etched to form isolatedtransistors down the length of the trench 54, as can be appreciated bythose skilled in the art.

[0048] While the invention may be susceptible to various modificationsand alternative forms, specific embodiments have been shown by way ofexample in the drawings and have been described in detail herein.However, it should be understood that the invention is not intended tobe limited to the particular forms disclosed. Rather, the invention isto cover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the followingappended claims.

What is claimed is:
 1. A memory cell having a vertically integratedtransistor comprising: a substrate having a trench and comprising eachof a first and second doped region located at the surface of thesubstrate and being coincident with the top of the trench; each of afirst and second sidewall spacer disposed within the trench such thateach of the first and second sidewall spacers is coincident to thebottom of the trench and one of the first and second doped regions; anda first oxide layer disposed within the trench and arranged to provide abarrier between each of the spacers and each of the doped regions. 2.The memory cell, as set forth in claim 1, wherein the substratecomprises a silicon substrate.
 3. The memory cell, as set forth in claim1, wherein each of the first and second sidewall spacers comprisepolysilicon.
 4. The memory cell, as set forth in claim 1, wherein thefirst oxide layer comprises silicon dioxide.
 5. The memory cell, as setforth in claim 1, comprising a wordline stack disposed within thetrench.
 6. The memory cell, as set forth in claim 5, wherein thewordline stack comprises a second oxide layer disposed within the trenchsuch that each of the first and second sidewall spacers is covered bythe second oxide layer.
 7. The memory cell, as set forth in claim 6,wherein the second oxide layer comprises an oxide-nitride-oxide (ONO)layer.
 8. The memory cell, as set forth in claim 6, wherein the wordlinestack comprises a polysilicon layer disposed on the second oxide layersuch that the trench is filled with the polysilicon layer.
 9. The memorycell, as set forth in claim 8, wherein the wordline stack comprises aconductive layer disposed on the polysilicon layer.
 10. The memory cell,as set forth in claim 9, wherein the conductive layer comprises a metallayer.
 11. The memory cell, as set forth in claim 10, wherein the metallayer comprises tungsten.
 12. The memory cell, as set forth in claim 10,wherein the conductive layer comprises a barrier layer disposed betweenthe polysilicon layer and the metal layer and configured to reduceelectron migration to the conductive layer.
 13. The memory cell, as setforth in claim 12, wherein the barrier layer comprises a metal nitride.14. The memory cell, as set forth in claim 13, wherein the barrier layercomprises tungsten nitride.
 15. The memory cell, as set forth in claim9, wherein the wordline stack comprises a nitride layer disposed on theconductive layer.
 16. The memory cell, as set forth in claim 1, whereinthe substrate comprises a third doped region located at the bottom ofthe trench.
 17. The memory cell, as set forth in claim 16, wherein thethird doped region extends through a length of the trench and isconfigured to form a bitline.
 18. The memory cell, as set forth in claim1, wherein the trench comprises a U-shaped trench.
 19. A method offabricating a memory device comprising the acts of: forming a trench ina substrate; disposing a first oxide layer in the trench; doping thesubstrate to form a first and second contact region on the surface ofthe substrate at the top of the trench; disposing a first polysiliconlayer over the first oxide layer, such that the first oxide layer isbetween the substrate and the polysilicon layer; etching the firstpolysilicon layer to form sidewall spacers within the trench, whereinthe sidewall spacers are adjacent to the contact regions; and forming awordline in the trench and over the first oxide layer.
 20. The method offabricating a memory device, as set forth in claim 19, wherein the actof forming a trench comprises the act of etching the substrate to form atrench.
 21. The method of fabricating a memory device, as set forth inclaim 19, wherein the act of forming a trench comprises the act offorming a U-shaped trench in the substrate.
 22. The method offabricating a memory device, as set forth in claim 19, wherein the actof disposing a first oxide layer comprises the act of disposing a firstoxide layer by chemical vapor deposition.
 23. The method of fabricatinga memory device, as set forth in claim 19, wherein the act of disposinga first oxide layer comprises the act of disposing silicon dioxide. 24.The method of fabricating a memory device, as set forth in claim 19,wherein the act of doping comprises the act of doping the substrate toform N+ contact regions.
 25. The method of fabricating a memory device,as set forth in claim 19, wherein the act of doping comprises the act ofdoping the substrate to form a third contact region at the bottom of thetrench.
 26. The method of fabricating a memory device, as set forth inclaim 19, wherein the act of etching the first polysilicon layercomprises the act of etching the first polysilicon layer such thanopening is formed at the bottom of the trench to expose the first oxidelayer.
 27. The method of fabricating a memory device, as set forth inclaim 19, wherein the act of forming a wordline comprises the act ofdisposing a second oxide layer in the trench and over the sidewallspacers.
 28. The method of fabricating a memory device, as set forth inclaim 27, wherein the act of disposing a second oxide layer comprisesthe act of disposing an oxide-nitride-oxide (ONO) layer.
 29. The methodof fabricating a memory device, as set forth in claim 27, wherein theact of forming the wordline comprises the act of disposing a secondpolysilicon layer over the second oxide layer such that the trench isfilled with the second polysilicon layer.
 30. The method of fabricatinga memory device, as set forth in claim 29, wherein the act of formingthe wordline stack comprises the act of disposing a conductive on thesecond polysilicon layer.
 31. The method of fabricating a memory device,as set forth in claim 30, wherein the act of disposing a conductivelayer comprises the act of disposing a metal layer.
 32. The method offabricating a memory device, as set forth in claim 31, wherein the actof disposing a metal layer comprises the act of disposing tungsten. 33.The method of fabricating a memory device, as set forth in claim 30,wherein the act of disposing a conductive layer comprises the act ofdisposing a barrier layer between the second polysilicon layer and themetal layer, wherein the barrier layer is configured to reduce electronmigration to the metal layer.
 34. The method of fabricating a memorydevice, as set forth in claim 33, wherein the act of disposing thebarrier layer comprises the act of disposing a metal nitride.
 35. Themethod of fabricating a memory device, as set forth in claim 33, whereinthe act of disposing the barrier layer comprises the act of disposing atungsten nitride.
 36. The method of fabricating a memory device, as setforth in claim 30, wherein the act of forming a wordline comprises theact of disposing a nitride layer on the conductive layer.
 37. A floatinggate transistor comprising: a trench formed in a substrate, the trenchcomprising a first sidewall, a second sidewall and a bottom; a firstfloating gate comprising a first polysilicon spacer disposed along thefirst sidewall; a second floating gate comprising a second polysiliconspacer disposed along the second sidewall and being electricallyisolated from the first polysilicon spacer; and a control gatecomprising a polysilicon wordline disposed on each of the first floatinggate and the second floating gate in a direction perpendicular to eachof the first and second polysilicon spacers.
 38. The floating gatetransistor, as set forth in claim 37, comprising a first oxide layerdisposed between the polysilicon wordline and each of the first floatinggate and the second floating gate.
 39. The floating gate transistor, asset forth in claim 37, wherein the first oxide layer comprises anoxide-nitride-oxide (ONO) layer.
 40. The floating gate transistor, asset forth in claim 37, comprising a second oxide layer disposed betweeneach of the sidewalls and each of the spacers.
 41. The floating gatetransistor, as set forth in claim 40, wherein the second oxide layercomprises silicon dioxide.
 42. The floating gate transistor, as setforth in claim 40, wherein the substrate comprises: a first doped regioncoincident with each of the first sidewall of the trench and the firstpolysilicon spacer; and a second doped region coincident with each ofthe second sidewall of the trench and the second polysilicon spacer. 43.The floating gate transistor, as set forth in claim 42, wherein thesubstrate comprises a third doped region coincident with each of thebottom of the trench, the first polysilicon spacer and the secondpolysilicon spacer.
 44. The floating gate transistor, as set forth inclaim 37, comprising a conductive layer disposed on the polysiliconwordline.
 45. The floating gate transistor, as set forth in claim 44,wherein the conductive layer comprises a metal layer.
 46. The floatinggate transistor, as set forth in claim 45, wherein the metal layercomprises tungsten.
 47. The floating gate transistor, as set forth inclaim 45, wherein the conductive layer comprises a barrier layerdisposed between the polysilicon wordline and the metal layer andconfigured to reduce electron migration to the polysilicon wordline. 48.The floating gate transistor, as set forth in claim 47, wherein thebarrier layer comprises a metal nitride.
 49. The floating gatetransistor, as set forth in claim 47, wherein the barrier layercomprises tungsten nitride.
 50. The floating gate transistor, as setforth in claim 44, comprising a nitride layer disposed on the conductivelayer.